By Henry Chang, Edoardo Charbon, Umakanta Choudhury, Alper Demir, Eric Felt, Edward Liu, Enrico Malavasi, Alberto Sangiovanni-Vincentelli, Iasson Vassiliou
Analog circuit layout is frequently the bottleneck whilst designing combined analog-digital platforms. A Top-Down, Constraint-Driven DesignMethodology for Analog built-in Circuits offers a brand new method in keeping with a top-down, constraint-driven layout paradigm that offers an answer to this challenge. this system has relevant merits: (1) it presents a excessive chance for the 1st silicon which meets all standards, and (2) it shortens the layout cycle.
A Top-Down, Constraint-Driven layout method for Analog IntegratedCircuits is a part of an ongoing learn attempt on the college of California at Berkeley within the electric Engineering and computing device Sciences division. Many school and scholars, prior and current, are engaged on this layout method and its assisting instruments. The relevant pursuits are: (1) constructing the layout technique, (2) constructing and making use of new instruments, and (3) `proving' the method via venture `industrial energy' layout examples. The paintings awarded this is neither a starting nor an result in the improvement of an entire top-down, constraint-driven layout method, yet really a step in its improvement.
This paintings is split into 3 components. bankruptcy 2 provides the layout technique besides origin fabric. Chapters 3-8 describe helping innovations for the technique, from behavioral simulation and modeling to circuit module turbines. ultimately, Chapters September 11 illustrate the method intimately by way of proposing the total layout cycle via 3 large-scale examples. those contain the layout of a present resource D/A converter, a Sigma-Delta A/D converter, and a video driving force process. bankruptcy 12 provides conclusions and present examine issues.
A Top-Down, Constraint-Driven layout method for Analog IntegratedCircuits can be of curiosity to analog and mixed-signal designers in addition to CAD instrument developers.
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Extra info for A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits
Given a library of n architectures, the first operation that must be performed is architectural selection. 16 Example Design Hierarchy for a Chip 2 35 Design Methodology Dotted line indicates failure Specifications Mappingof Specifications Description of Arch. I •• • Simulators -----1 I Pep Beh I r-----:=--_~~~~~~l-~ Description of Archn r- I I I I I I I ~ Description of Arch i Map Arch. i Map to lowernode I ••• ~~~~~~J SpecSheet I 1~~v~~_J ••• Map to lower noden 1 I I Netlist ~-- -- I I L.. 17 DesignMethodology S ecs.
A newer technique  based on behavioral simulation directlycalculates the circuit performance specifications, INL and DNL. 05 LSB. 15showsthe standarddesignhierarchy. At the topof thedesign hierarchy is a top node which couldrepresent an entire chip or just part of a chip. From this top node thereis a set of direct descendent lower nodes,representing a first-level decomposition of the upper node. From these lower nodes the graph continues to be expanded. The Design Methodology 33 Node 0 Arc 0 Arc n Arc I ••• ...
Macromodels forlineartimeinvariant circuits can be generated through the use of techniques such as symbolic analysis , asymptotic waveform evaluation  and block Lanczos algorithm . However, we do not believe that automatic generation of macromodels for nonlinear circuitsin general is feasible. Macromodels composed of interconnections of basic circuit primitives available in circuit simulators are convenient in the sense that a circuit simulator such as SPICE can be used withoutany changes.