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,' X:[. ] :� - - __ - Figure 8: : ____ __ I I 1 ; � I I •• 1 *[. . ] II:] __ ___ I I I 1: I " " " " �---------------------- I I I I 1 : : ::::::: : : :::::::::::::::::::::: - __ Translation of the : switch I Process generated to directly implement each probe by merging together, with an OR operator, each input wire of a passive port.

Indeed, t he function that links the stabilization time of the input and output of a level-sensitive latch is monotonic but not linear (1)(2). The new iterative procedure to determine the optimal clocking parameters in a circuit containing level-sensitive latches is described in this section. Each iteration step in the procedure can be performed in time linearly proportional to the circuit size. At each step, a near-optimal solution is available. Indeed, the solution produced always satisfies the timing requirements and leads to the shortest cycle time, given the current retardation values set at the latches At the end of the it.

Jouppi, "Timing Analysis for NMOS VLSI," Proceedings of the 20th Design A uto matio n Co nfere nce, 1983, pp. 411-418. Szymanski, "LEAD OUT: A Static Timing Analyzer for MOS Circ uits, " Proceedings of the 1986 IEEE I nter natio nal Conference on CAD, Santa Clara, California, November 1986, pp. 130-133. R. C. Rumin, "Timing Analysis and Verifica­ tion of Digital MOS C ircuits ," Proceedings of CompEuro 1987, Hamburg, Federal Republic of Germany, May 1987, pp. 242-245. G. Szymanski, "Private Communication," McGill, Montreal, Canada, April 1987.

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